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dsPIC30F3010/3011

DS70141F-page 46

2010 Microchip Technology Inc.

5.1

Interrupt Priority

The user-assignable Interrupt Priority (IP<2:0>) bits for

each individual interrupt source are located in the

3 LSbs of each nibble, within the IPCx register(s). Bit

3 of each nibble is not used and is read as a ‘0’. These

bits define the priority level assigned to a particular

interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user-assigned priority level, a

means is provided to assign priority within a given level.

This method is called “Natural Order Priority”.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC DSC devices and their

associated vector numbers.

The ability for the user to assign every interrupt to one

of seven priority levels implies that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PWM Fault

A Interrupt can be given a priority of 7. The INT0

(external interrupt 0) may be assigned to priority

Level 1, thus giving it a very low effective priority.

TABLE 5-1:

INTERRUPT VECTOR TABLE

Note:

The user-assignable priority levels start at

0, as the lowest priority, and Level 7, as

the highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2:The natural order priority number is the

same as the INT number.

Interrupt

Number

Vector

Number

Interrupt Source

Highest Natural Order Priority

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

T1 – Timer1

IC2 – Input Capture 2

OC2 – Output Compare 2

T2 – Timer2

T3 – Timer3

SPI1

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC – ADC Convert Done

NVM – NVM Write Complete

SI2C – I2C Slave Interrupt

MI2C – I2C Master Interrupt

Input Change Interrupt

INT1 – External Interrupt 1

IC7 – Input Capture 7

IC8 – Input Capture 8

OC3 – Output Compare 3(1)

OC4 – Output Compare 4(1)

T4 – Timer4

T5 – Timer5

INT2 – External Interrupt 2

U2RX – UART2 Receiver(1)

U2TX – UART2 Transmitter(1)

Reserved

PWM – PWM Period Match

QEI – QEI Interrupt

Reserved

FLTA – PWM Fault A

Reserved

45-53

53-61

Reserved

Lowest Natural Order Priority

Note 1:

Available on dsPIC30F3011 only

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